A Novel Design of 9-bit Pipeline Adc
نویسندگان
چکیده
In this paper, design of low power, 9-bit pipeline ADC architecture is introduced .A pipeline ADC architecture has a 3-stage pipeline ADC with 3-bit flash ADC followed by a 3-bit DAC at each stage. A novel approach to design a 3-bit ADC is implemented; this design offers less number of comparator and low power consumption with less circuit complexity based on this idea a 9-bit ADC is simulated in cadence virtuoso in 90 nm technology the maximum sampling speed is achieved by 670 MS/s. The power consumption of pipeline ADC is 39mW.
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